From 2704416c384d5e2990621b15be01f37f4f9c49e0 Mon Sep 17 00:00:00 2001 From: NIIBE Yutaka Date: Mon, 23 May 2016 20:15:47 +0900 Subject: [PATCH] Fix PSR handling (ORRS instruction changes PSR) --- ChangeLog | 4 ++++ chopstx.c | 18 +++++++++--------- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/ChangeLog b/ChangeLog index 55bc7e1..6e63652 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,7 @@ +2016-05-23 NIIBE Yutaka + + * chopst.x (chx_sched) [__ARM_ARCH_6M__]: Maintain PSR. + 2016-05-23 NIIBE Yutaka * chopstx.c (chopstx_poll): Fix a race. Check COUNTER. diff --git a/chopstx.c b/chopstx.c index ac0d49b..19316ac 100644 --- a/chopstx.c +++ b/chopstx.c @@ -727,7 +727,7 @@ chx_request_preemption (uint16_t prio) * AAPCS: ARM Architecture Procedure Call Standard * * Returns: - * 1 on erroneous wakeup. + * 1 on wakeup by others. * 0 on normal wakeup. * -1 on cancellation. */ @@ -855,11 +855,11 @@ chx_sched (uint32_t yield) "lsl r1, r0, #23\n\t" "bcc 2f\n\t" /**/ - "msr APSR_nzcvq, r0\n\t" - "ldr r0, [sp, #24]\n\t" + "ldr r2, [sp, #24]\n\t" "mov r1, #1\n\t" - "orr r0, r1\n\t" /* Ensure Thumb-mode */ - "str r0, [sp, #32]\n\t" + "orr r2, r1\n\t" /* Ensure Thumb-mode */ + "str r2, [sp, #32]\n\t" + "msr APSR_nzcvq, r0\n\t" /**/ "ldr r0, [sp, #20]\n\t" "mov lr, r0\n\t" @@ -869,11 +869,11 @@ chx_sched (uint32_t yield) "add sp, #16\n\t" "pop {pc}\n" "2:\n\t" - "msr APSR_nzcvq, r0\n\t" - "ldr r0, [sp, #24]\n\t" + "ldr r2, [sp, #24]\n\t" "mov r1, #1\n\t" - "orr r0, r1\n\t" /* Ensure Thumb-mode */ - "str r0, [sp, #28]\n\t" + "orr r2, r1\n\t" /* Ensure Thumb-mode */ + "str r2, [sp, #28]\n\t" + "msr APSR_nzcvq, r0\n\t" /**/ "ldr r0, [sp, #20]\n\t" "mov lr, r0\n\t"