deon/chopstx
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Version 0.02

Browse Source
This commit is contained in:
NIIBE Yutaka
2013-11-08 11:37:53 +09:00
parent e957d1aff8
commit 21c3f461c5
6 changed files with 55 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
ChangeLog
View File

@@ -1,3 +1,13 @@
2013-11-08 Niibe Yutaka <gniibe@fsij.org>
* Version 0.02.
* doc/chopstx.texi (VERSION): 0.02.
* example-cdc/usb_stm32f103.c: Updated from NeuG.
* chopstx.c (CPU_EXCEPTION_PRIORITY_SYSTICK): Equals to
CPU_EXCEPTION_PRIORITY_INTERRUPT.
2013-11-03 Niibe Yutaka <gniibe@fsij.org> 2013-11-03 Niibe Yutaka <gniibe@fsij.org>
* Version 0.01. * Version 0.01.

12
NEWS
View File

@@ -1,5 +1,17 @@
NEWS - Noteworthy changes NEWS - Noteworthy changes
* Major changes in Chopstx 0.02
Released 2013-11-08, by NIIBE Yutaka
** Bug fix of priority
There was a severe bug about the configuraion of priority setting of
exceptions. As we don't use any inter-lock between interrupts hander
and timer expiration handler, these priorities should be equal. If
not, timer expiration handler might interrupt the execution of
interrupts handers.
* Major changes in Chopstx 0.01 * Major changes in Chopstx 0.01
Released 2013-11-03, by NIIBE Yutaka Released 2013-11-03, by NIIBE Yutaka

4
README
View File

@@ -1,6 +1,6 @@
Chopstx - Threads and only Threads Chopstx - Threads and only Threads
Version 0.01 Version 0.02
2013-11-03 2013-11-08
Niibe Yutaka Niibe Yutaka
Flying Stone Technology Flying Stone Technology

5
chopstx.c
View File

@@ -54,9 +54,8 @@
* Prio 0x30: svc * Prio 0x30: svc
* --------------------- * ---------------------
* Prio 0x40: thread temporarily inhibiting schedule for critical region * Prio 0x40: thread temporarily inhibiting schedule for critical region
* Prio 0x50: systick
* ... * ...
* Prio 0xb0: external interrupt * Prio 0xb0: systick, external interrupt
* Prio 0xc0: pendsv * Prio 0xc0: pendsv
*/ */
@@ -65,8 +64,8 @@
#define CPU_EXCEPTION_PRIORITY_SVC 0x30 #define CPU_EXCEPTION_PRIORITY_SVC 0x30
#define CPU_EXCEPTION_PRIORITY_INHIBIT_SCHED 0x40 #define CPU_EXCEPTION_PRIORITY_INHIBIT_SCHED 0x40
#define CPU_EXCEPTION_PRIORITY_SYSTICK 0x50
/* ... */ /* ... */
#define CPU_EXCEPTION_PRIORITY_SYSTICK CPU_EXCEPTION_PRIORITY_INTERRUPT
#define CPU_EXCEPTION_PRIORITY_INTERRUPT 0xb0 #define CPU_EXCEPTION_PRIORITY_INTERRUPT 0xb0
#define CPU_EXCEPTION_PRIORITY_PENDSV 0xc0 #define CPU_EXCEPTION_PRIORITY_PENDSV 0xc0

2
doc/chopstx.texi
View File

@@ -1,7 +1,7 @@
\input texinfo @c -*-texinfo-*- \input texinfo @c -*-texinfo-*-
@c %**start of header @c %**start of header
@setfilename chopstx.info @setfilename chopstx.info
@set VERSION 0.01 @set VERSION 0.02
@settitle Chopstx Reference Manual @settitle Chopstx Reference Manual
@c Unify some of the indices. @c Unify some of the indices.
@syncodeindex tp fn @syncodeindex tp fn

67
example-cdc/usb_stm32f103.c
View File

@@ -93,8 +93,8 @@ static struct DATA_INFO *const data_p = &data_info;
/* Buffer Table address register */ /* Buffer Table address register */
#define BTABLE ((volatile uint16_t *)(REG_BASE + 0x50)) #define BTABLE ((volatile uint16_t *)(REG_BASE + 0x50))
#define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ #define ISTR_CTR (0x8000) /* Correct TRansfer (read-only bit) */
#define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ #define ISTR_OVR (0x4000) /* OVeR/underrun (clear-only bit) */
#define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ #define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */
#define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ #define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */
#define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ #define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */
@@ -105,8 +105,7 @@ static struct DATA_INFO *const data_p = &data_info;
#define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ #define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */
#define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ #define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
#define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ #define CLR_OVR (~ISTR_OVR) /* clear OVeR/underrun bit*/
#define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/
#define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ #define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */
#define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ #define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */
#define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ #define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */
@@ -115,7 +114,7 @@ static struct DATA_INFO *const data_p = &data_info;
#define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ #define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */
#define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ #define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */
#define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ #define CNTR_OVRM (0x4000) /* OVeR/underrun Mask */
#define CNTR_ERRM (0x2000) /* ERRor Mask */ #define CNTR_ERRM (0x2000) /* ERRor Mask */
#define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ #define CNTR_WKUPM (0x1000) /* WaKe UP Mask */
#define CNTR_SUSPM (0x0800) /* SUSPend Mask */ #define CNTR_SUSPM (0x0800) /* SUSPend Mask */
@@ -391,19 +390,19 @@ usb_interrupt_handler (void)
{ {
uint16_t istr_value = st103_get_istr (); uint16_t istr_value = st103_get_istr ();
if (istr_value & ISTR_CTR) if ((istr_value & ISTR_CTR))
usb_handle_transfer (); usb_handle_transfer ();
if (istr_value & ISTR_RESET) if ((istr_value & ISTR_RESET))
{ {
st103_set_istr (CLR_RESET); st103_set_istr (CLR_RESET);
usb_cb_device_reset (); usb_cb_device_reset ();
} }
if (istr_value & ISTR_DOVR) if ((istr_value & ISTR_OVR))
st103_set_istr (CLR_DOVR); st103_set_istr (CLR_OVR);
if (istr_value & ISTR_ERR) if ((istr_value & ISTR_ERR))
st103_set_istr (CLR_ERR); st103_set_istr (CLR_ERR);
} }
@@ -539,7 +538,7 @@ static int std_get_status (uint8_t req,
uint8_t endpoint = (index & 0x0f); uint8_t endpoint = (index & 0x0f);
uint16_t status; uint16_t status;
if ((index & 0x70) != 0 || endpoint == ENDP0) if ((index & 0x70) || endpoint == ENDP0)
return USB_UNSUPPORT; return USB_UNSUPPORT;
if ((index & 0x80)) if ((index & 0x80))
@@ -938,35 +937,29 @@ usb_handle_transfer (void)
uint16_t istr_value; uint16_t istr_value;
uint8_t ep_index; uint8_t ep_index;
while (((istr_value = st103_get_istr ()) & ISTR_CTR) != 0) while (((istr_value = st103_get_istr ()) & ISTR_CTR))
{ {
ep_index = (istr_value & ISTR_EP_ID); ep_index = (istr_value & ISTR_EP_ID);
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
ep_value = st103_get_epreg (ep_index);
if (ep_index == 0) if (ep_index == 0)
{ {
if ((istr_value & ISTR_DIR) == 0) if ((ep_value & EP_CTR_TX))
{ /* DIR = 0 */ {
/* DIR = 0 => IN int */ st103_ep_clear_ctr_tx (ep_index);
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
st103_ep_clear_ctr_tx (ENDP0);
handle_in0 (); handle_in0 ();
} }
else
{ /* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep_value = st103_get_epreg (ENDP0); if ((ep_value & EP_CTR_RX))
if ((ep_value & EP_SETUP) != 0) {
{ st103_ep_clear_ctr_rx (ep_index);
st103_ep_clear_ctr_rx (ENDP0);
handle_setup0 (); if ((ep_value & EP_SETUP))
} handle_setup0 ();
else if ((ep_value & EP_CTR_RX) != 0) else
{ handle_out0 ();
st103_ep_clear_ctr_rx (ENDP0);
handle_out0 ();
}
} }
if (dev_p->state == STALLED) if (dev_p->state == STALLED)
@@ -974,11 +967,7 @@ usb_handle_transfer (void)
} }
else else
{ {
/* Decode and service non control endpoints interrupt */ if ((ep_value & EP_CTR_RX))
/* process related endpoint register */
ep_value = st103_get_epreg (ep_index);
if ((ep_value & EP_CTR_RX) != 0)
{ {
st103_ep_clear_ctr_rx (ep_index); st103_ep_clear_ctr_rx (ep_index);
switch ((ep_index - 1)) switch ((ep_index - 1))
@@ -993,7 +982,7 @@ usb_handle_transfer (void)
} }
} }
if ((ep_value & EP_CTR_TX) != 0) if ((ep_value & EP_CTR_TX))
{ {
st103_ep_clear_ctr_tx (ep_index); st103_ep_clear_ctr_tx (ep_index);
switch ((ep_index - 1)) switch ((ep_index - 1))