Add RISC-V 32 IMAC support.

Signed-off-by: NIIBE Yutaka <gniibe@fsij.org>

mcu/chx-gd32vf103.c

@@ -0,0 +1,22 @@
+#include <stdint.h>
+#include <mcu/gd32vf103.h>
+
+asm (
+	".equ	wfe,0x810\n\t"    /* Not used (yet). */
+	".equ	sleepvalue,0x811" /* Not used (yet). */
+);
+
+extern int chx_allow_sleep;
+
+void
+chx_sleep_mode (int how)
+{
+  /*TBD*/
+  (void)how;
+}
+
+void
+chx_prepare_sleep_mode (void)
+{
+  /*TBD*/
+}

mcu/clk_gpio_init-gd32vf103.c

@@ -0,0 +1,77 @@
+#include <stdint.h>
+#include <mcu/gd32vf103.h>
+
+static void __attribute__((used,section(".text.startup.1")))
+clock_init (void)
+{
+  /* HXTAL setup */
+  RCU->CTL |= RCU_CTL_HXTALEN;
+  while (!(RCU->CTL & RCU_CTL_HXTALSTB))
+    ;
+
+  RCU->CFG0 &= ~RCU_CFG0_AHB_APB1_APB2_MASK;
+
+  /* CK_AHB = CK_SYS */
+  RCU->CFG0 |= RCU_CFG0_AHB_CKSYS_DIV1;
+  /* CK_APB2 = CK_AHB */
+  RCU->CFG0 |= RCU_CFG0_APB2_CKAHB_DIV1;
+  /* CK_APB1 = CK_AHB/2 */
+  RCU->CFG0 |= RCU_CFG0_APB1_CKAHB_DIV2;
+
+  /* CK_ADC, CK_TIMER1xxx, CK_TIMER0, CK_I2S */
+
+  /* PLL setup */
+  RCU->CFG0 &= ~RCU_CFG0_PLLSRC_PLLMF_MASK;
+  RCU->CFG0 |= RCU_CFG0_PLL_MUL_VALUE | RCU_CFG0_PLLSRC_HXTAL;
+
+  RCU->CFG1 &= ~RCU_CFG1_PREDV0SEL_MASK;
+  RCU->CFG1 |= RCU_CFG1_PREDV0SEL_HXTAL;
+
+  RCU->CTL |= RCU_CTL_PLLEN;
+
+  while (!(RCU->CTL & RCU_CTL_PLLSTB))
+    ;
+
+  /* Select PLL as system clock */
+  RCU->CFG0 &= ~RCU_CFG0_SCS_MASK;
+  RCU->CFG0 |= RCU_CFG0_CKSYSSRC_PLL;
+
+  /* Wait until PLL is selected as system clock */
+  while (!(RCU->CFG0 & RCU_CFG0_SCSS_PLL))
+    ;
+
+  /* Stop IRC8M */
+  RCU->CTL &= ~RCU_CTL_IRC8MEN;
+
+  /* Flash setup: TBD */
+}
+
+static void __attribute__((used,section(".text.startup.1")))
+gpio_init (void)
+{
+  RCU->APB2EN  |= RCU_APB2_GPIO;
+  RCU->APB2RST = RCU_APB2_GPIO;
+  RCU->APB2RST = 0;
+
+#ifdef AFIO_MAPR_SOMETHING
+  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
+#endif
+
+  /* LED is mandatory.  We configure it always.  */
+  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
+  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
+  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
+
+  /* If there is USB enabler pin and it's independent, we configure it.  */
+#if defined(GPIO_USB) && defined(VAL_GPIO_USB_ODR)
+  GPIO_USB->ODR = VAL_GPIO_USB_ODR;
+  GPIO_USB->CRH = VAL_GPIO_USB_CRH;
+  GPIO_USB->CRL = VAL_GPIO_USB_CRL;
+#endif
+
+#ifdef GPIO_OTHER
+  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
+  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
+  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
+#endif
+}

mcu/gd32vf103.h

@@ -0,0 +1,56 @@
+struct RCU {
+  volatile uint32_t CTL;
+  volatile uint32_t CFG0;
+  volatile uint32_t INT;
+  volatile uint32_t APB2RST;
+  volatile uint32_t APB1RST;
+  volatile uint32_t AHBEN;
+  volatile uint32_t APB2EN;
+  volatile uint32_t APB1EN;
+  volatile uint32_t BDCTL;
+  volatile uint32_t RSTSCK;
+  volatile uint32_t AHBRST;
+  volatile uint32_t CFG1;
+  uint32_t rsv;
+  volatile uint32_t DSV;
+};
+static struct RCU *const RCU = (struct RCU *)0x40021000;
+
+#define RCU_CTL_HXTALEN  0x00010000
+#define RCU_CTL_HXTALSTB 0x00020000
+#define RCU_CTL_PLLSTB   0x02000000
+#define RCU_CTL_PLLEN    0x01000000
+#define RCU_CTL_IRC8MEN  0x00000001
+
+#define RCU_CFG0_ADC_MASK           0x0000c000
+#define RCU_CFG0_AHB_APB1_APB2_MASK 0x00003ff0
+#define RCU_CFG0_AHB_CKSYS_DIV1     0x00000000
+#define RCU_CFG0_APB2_CKAHB_DIV1    0x00000000
+#define RCU_CFG0_APB1_CKAHB_DIV2    0x00000400
+#define RCU_CFG0_PLLSRC_PLLMF_MASK  0x203d0000
+#define RCU_CFG0_PLL_MUL12          0x00280000
+#define RCU_CFG0_PLLSRC_HXTAL       0x00010000
+#define RCU_CFG0_SCS_MASK           0x00000003
+#define RCU_CFG0_SCSS_PLL           0x00000008
+#define RCU_CFG0_CKSYSSRC_PLL       0x00000002
+
+#define RCU_CFG1_PREDV0SEL_MASK     0x00010000
+#define RCU_CFG1_PREDV0SEL_HXTAL    0x00000000
+
+#define RCU_APB2_GPIOA  0x00000004
+#define RCU_APB2_GPIOB  0x00000008
+#define RCU_APB2_GPIOC  0x00000010
+
+/* Semantics is exactly same as STM32F103.  */
+struct GPIO {
+  volatile uint32_t CRL;
+  volatile uint32_t CRH;
+  volatile uint32_t IDR;
+  volatile uint32_t ODR;
+  volatile uint32_t BSRR;
+  volatile uint32_t BRR;
+  volatile uint32_t LCKR;
+};
+static struct GPIO *const GPIOA = (struct GPIO *)0x40010800;
+static struct GPIO *const GPIOB = (struct GPIO *)0x40010C00;
+static struct GPIO *const GPIOC = (struct GPIO *)0x40011000;