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stm32l4: Enable PWR module and USV-bit in CR2.

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This commit is contained in:
NIIBE Yutaka
2019-04-18 19:13:23 +09:00
parent 359082f80a
commit 1d2aacd0a4
2 changed files with 8 additions and 1 deletions
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5
mcu/clk_gpio_init-stm32l.c
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@@ -61,6 +61,11 @@ clock_init (void)
(0x00 << 2) | /* PCLK for USART2 */ (0x00 << 2) | /* PCLK for USART2 */
(0x00 << 0) ); /* PCLK for USART1 */ (0x00 << 0) ); /* PCLK for USART1 */
/* Enable PWR clock */
RCC->APB1ENR1 |= (1 << 28);
RCC->APB1RSTR1 = (1 << 28);
RCC->APB1RSTR1 = 0;
/* Enable HSI48 clock */ /* Enable HSI48 clock */
RCC->CRRCR |= 1; RCC->CRRCR |= 1;
while ((RCC->CRRCR & 0x02) == 0) while ((RCC->CRRCR & 0x02) == 0)

4
mcu/sys-stm32l4.c
View File

@@ -65,7 +65,9 @@ static struct CRS *const CRS = ((struct CRS *)(APB1PERIPH_BASE + 0x6000));
void void
usb_lld_sys_init (void) usb_lld_sys_init (void)
{ {
if ((RCC->APB1ENR1 & RCC_APB1_1_USB) PWR->CR2 |= (1 << 10); /* USB supply valid */
if ((RCC->APB1ENR1 & RCC_APB1_1_USB)
&& (RCC->APB1RSTR1 & RCC_APB1_1_USB) == 0) && (RCC->APB1RSTR1 & RCC_APB1_1_USB) == 0)
/* Make sure the device is disconnected, even after core reset. */ /* Make sure the device is disconnected, even after core reset. */
{ {